{"id":353781,"date":"2026-01-12T20:30:27","date_gmt":"2026-01-12T15:00:27","guid":{"rendered":"https:\/\/forumias.com\/blog\/?p=353781"},"modified":"2026-01-14T10:24:05","modified_gmt":"2026-01-14T04:54:05","slug":"design-linked-incentive-scheme","status":"publish","type":"post","link":"https:\/\/forumias.com\/blog\/design-linked-incentive-scheme\/","title":{"rendered":"Design Linked Incentive Scheme"},"content":{"rendered":"<p><strong>Context-<\/strong> Semiconductor chips are critical for healthcare, transport, communications, defence, space, AI, and digital infrastructure. Global demand is rising rapidly due to digitalisation and automation.<\/p>\n<p>However, Semiconductor manufacturing is concentrated in a few geographies, making global supply chains fragile and disruption-prone. India aims to emerge as a strategic, reliable semiconductor hub through- <strong>Semicon India Programme<\/strong> and <strong>India Semiconductor Mission (ISM). Design Linked Incentive Scheme.<\/strong><\/p>\n<p><img data-recalc-dims=\"1\" loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-353973\" src=\"https:\/\/i0.wp.com\/forumias.com\/blog\/wp-content\/uploads\/2026\/01\/Design-Linked-Incentive-Scheme.png?resize=482%2C320&#038;ssl=1\" alt=\"Design Linked Incentive Scheme\" width=\"482\" height=\"320\" srcset=\"https:\/\/i0.wp.com\/forumias.com\/blog\/wp-content\/uploads\/2026\/01\/Design-Linked-Incentive-Scheme.png?resize=300%2C199&amp;ssl=1 300w, https:\/\/i0.wp.com\/forumias.com\/blog\/wp-content\/uploads\/2026\/01\/Design-Linked-Incentive-Scheme.png?resize=1024%2C680&amp;ssl=1 1024w, https:\/\/i0.wp.com\/forumias.com\/blog\/wp-content\/uploads\/2026\/01\/Design-Linked-Incentive-Scheme.png?resize=768%2C510&amp;ssl=1 768w, https:\/\/i0.wp.com\/forumias.com\/blog\/wp-content\/uploads\/2026\/01\/Design-Linked-Incentive-Scheme.png?w=1280&amp;ssl=1 1280w\" sizes=\"auto, (max-width: 482px) 100vw, 482px\" \/><\/p>\n<h2><strong>What is the Strategic Importance of Fabless Chip Design?<\/strong><strong>\u00a0<\/strong><\/h2>\n<p>Fabless semiconductor design represents the highest-value segment of the semiconductor value chain. Fabless semiconductor design represents the highest-value segment of the semiconductor value chain.<\/p>\n<p>A robust fabless model offers the following advantages:<\/p>\n<ul>\n<li>High value addition<\/li>\n<li>Lower capital expenditure compared to fabs<\/li>\n<li>Ownership of IP<\/li>\n<li>Reduced imports<\/li>\n<li>Attraction of manufacturing<\/li>\n<li>Long-term technological leadership<\/li>\n<\/ul>\n<h2><strong>What is the Design Linked Incentive (DLI) Scheme?<\/strong><\/h2>\n<p>It was launched in December 2021 under the <strong>Semicon India Programme<\/strong>. It is implemented by <strong>MeitY<\/strong>, with <strong>C-DAC<\/strong> as the nodal agency.<\/p>\n<p>Its objective is to <strong>build a self-reliant, indigenous semiconductor design ecosystem<\/strong> and <strong>support startups and MSMEs from idea to silicon to productisation<\/strong>.<\/p>\n<p>Eligibility under DLI Scheme- Startups (as per DPIIT, 2019), MSMEs (as per MSME Ministry notification, 2020) and Domestic companies owned by resident Indian citizens (FDI Policy, 2017).<\/p>\n<p>Scope of support covers the full design lifecycle of Integrated Circuits (ICs), Chipsets, Systems-on-Chip (SoCs) and Systems and IP cores.<\/p>\n<p>DLI aims to &#8211; Increase indigenous semiconductor content, Reduce import dependence, and Strengthen supply-chain resilience.<\/p>\n<h2><strong>Financial Incentives under DLI<\/strong><\/h2>\n<table style=\"width: 98.4015%;\" width=\"624\">\n<tbody>\n<tr>\n<td style=\"width: 39.7764%;\" width=\"244\"><strong>\u00a0<\/strong><\/p>\n<p><strong>Product Design Linked Incentive<\/strong><\/td>\n<td style=\"width: 97.4441%;\" width=\"380\"><strong>Reimbursement <\/strong>up to 50% of eligible expenditure<\/p>\n<p><strong>Cap: <\/strong>\u20b915 crore per application<\/p>\n<p>Applicable to ICs, chipsets, SoCs, systems, and IP cores<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 39.7764%;\" width=\"244\"><strong>\u00a0<\/strong><\/p>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>Deployment Linked Incentive<\/strong><\/td>\n<td style=\"width: 97.4441%;\" width=\"380\"><strong>Incentive of 6%\u20134% <\/strong>of net sales turnover for 5 years<\/p>\n<p><strong>Cap:<\/strong> \u20b930 crore per application<\/p>\n<p>Minimum cumulative net sales (Years 1\u20135): \u20b91 crore for startups\/MSMEs and \u20b95 crore for other domestic companies<\/p>\n<p>Design must be successfully deployed in electronic products<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><strong>What are the Institutional Frameworks Supporting Semiconductor Design?<\/strong><\/h2>\n<table style=\"width: 98.8558%;\" width=\"624\">\n<tbody>\n<tr>\n<td style=\"width: 34.984%;\" width=\"206\"><strong>\u00a0<\/strong><\/p>\n<p><strong>\u00a0<\/strong><\/p>\n<p><strong>Ministry of Electronics and IT (MeitY)<\/strong><\/td>\n<td style=\"width: 102.875%;\" width=\"418\">\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Policy leadership and coordination<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Anchors national semiconductor initiatives<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Introduced DLI to help Indian firms move up the value chain<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 34.984%;\" width=\"206\">&nbsp;<\/p>\n<p><strong>Semicon India Programme (SIM)<\/strong><\/p>\n<p>&nbsp;<\/td>\n<td style=\"width: 102.875%;\" width=\"418\">\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Total outlay: \u20b976,000 crore<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Supports manufacturing, design, and display ecosystems<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Provides end-to-end support from design to productisation<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 34.984%;\" width=\"206\">&nbsp;<\/p>\n<p><strong>Chips to Startup (C2S) Programme<\/strong><\/p>\n<p>&nbsp;<\/td>\n<td style=\"width: 102.875%;\" width=\"418\">\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Capacity-building initiative across academic institutions<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Target: 85,000 industry-ready professionals<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Covers B.Tech, M.Tech, and PhD levels in chip design<\/td>\n<\/tr>\n<tr>\n<td style=\"width: 34.984%;\" width=\"206\"><strong>Microprocessor Development Programme<\/strong><\/td>\n<td style=\"width: 102.875%;\" width=\"418\">\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Implemented by C-DAC, IIT Madras, IIT Bombay<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Delivered indigenous open-source processors: VEGA, SHAKTI and AJIT<\/p>\n<p>\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 Strengthens self-reliance in CPU architectures<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<h2><strong>What are the success stories under the DLI Scheme?<\/strong><\/h2>\n<p>24 chip-design projects sanctioned (e.g., video surveillance, drones, energy meters, microprocessors, satellite communications, IoT SoCs). 95 companies provided access to industry-grade EDA tools<\/p>\n<p>Notable Beneficiaries<\/p>\n<p><strong>Vervesemi Microelectronics-<\/strong> 110+ IPs, 25 IC variants, 10 patents. Motor-control chips for consumer appliances and EVs. Pilot-lot sampling completed; global customers engaged<\/p>\n<p><strong>InCore Semiconductors-<\/strong> Indigenous RISC-V processor IPs. Silicon-proven across 180 nm to 16 nm nodes. Targeting entry-level smartphones and edge AI.<\/p>\n<p><strong>Netrasemi-<\/strong> Designed India\u2019s first indigenous AI SoC at 12 nm. Applications in surveillance, robotics, drones. Strong VC backing; multiple tape-outs planned.<\/p>\n<h2><strong>Conclusion<\/strong><\/h2>\n<p>There has been a Strategic Impact of the DLI Scheme. It anchors India in the most value-intensive segment of semiconductors design, reduces dependence on imported IPs and chips and enhances resilience against geopolitical and supply-chain disruptions.<\/p>\n<p>With silicon-validated designs moving toward mass manufacturing and deployment, India is emerging as a credible global semiconductor design player and strengthening its self-reliant ecosystem.<\/p>\n<p><strong>Source: <\/strong><a href=\"https:\/\/www.pib.gov.in\/PressNoteDetails.aspx?NoteId=156811&amp;ModuleId=3&amp;reg=3&amp;lang=1\"><strong>PIB<\/strong><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Context- Semiconductor chips are critical for healthcare, transport, communications, defence, space, AI, and digital infrastructure. Global demand is rising rapidly due to digitalisation and automation. However, Semiconductor manufacturing is concentrated in a few geographies, making global supply chains fragile and disruption-prone. India aims to emerge as a strategic, reliable semiconductor hub through- Semicon India Programme&hellip; <a class=\"more-link\" href=\"https:\/\/forumias.com\/blog\/design-linked-incentive-scheme\/\">Continue reading <span class=\"screen-reader-text\">Design Linked Incentive Scheme<\/span><\/a><\/p>\n","protected":false},"author":10320,"featured_media":353973,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"jetpack_post_was_ever_published":false,"footnotes":""},"categories":[1230],"tags":[216,3590,242],"class_list":["post-353781","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-9-pm-daily-articles","tag-gs-paper-3","tag-pib","tag-science-and-technology","entry"],"jetpack_featured_media_url":"https:\/\/i0.wp.com\/forumias.com\/blog\/wp-content\/uploads\/2026\/01\/Design-Linked-Incentive-Scheme.png?fit=1280%2C850&ssl=1","views":"","jetpack_sharing_enabled":true,"_links":{"self":[{"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/posts\/353781","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/users\/10320"}],"replies":[{"embeddable":true,"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/comments?post=353781"}],"version-history":[{"count":0,"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/posts\/353781\/revisions"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/media\/353973"}],"wp:attachment":[{"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/media?parent=353781"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/categories?post=353781"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/forumias.com\/blog\/wp-json\/wp\/v2\/tags?post=353781"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}